1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device using a porous low-dielectric-constant insulating film.
2. Background Art
With the miniaturization and high-speed operation of semiconductor devices in recent years, wiring structures have been more multi-layered. However, in such a trend, signal delay due to increase in wiring resistance and parasitic capacitance between wirings and between wiring layers causes problems. Since signal delay T is proportional to the product of wiring resistance R and parasitic capacitance C, the resistance of the wiring layer as well as parasitic capacitance must be lowered in order to minimize signal delay T.
In order to lower wiring resistance R, wiring materials having a low resistance must be used. Specifically, the shift from the conventional aluminum (Al) wiring to copper (Cu) wiring is considered.
On the other hand, the parasitic capacitance C between wiring layers has the relationship to the specific dielectric constant ∈ of the interlayer insulating film formed between wiring layers, the distance d between the wiring layers, and the side-face area S of the wiring layer as C=(∈×S)/d. Therefore, in order to lower the capacitance C, the dielectric constant of the interlayer insulating film must be lowered.
Examples of conventionally known interlayer insulating films include an SiOF film formed using a CVD (chemical vapor deposition) method. The specific dielectric constant of the SiOF film is about 3.3, which is lower than the specific dielectric constant of an SiO2 film of about 3.9. However, if the specific dielectric constant must be further lowered, it is difficult to use the SiOF film practically because the stability of the film is insufficient.
Therefore, the application of SOG (spin on glass) films or organic polymer films to the interlayer insulating film has been examined. It has been known that the specific dielectric constant of these films can be lowered to about 1.9 if they are made porous (e.g., refer to Japanese Patent Laid-Open No. 11-330069).
A conventional method for forming a copper wiring using a porous low-dielectric-constant insulating film (porous low-k film) will be described referring to FIGS. 12 to 15. In there drawings, the parts denoted by the same reference numerals are the same parts.
First, as FIG. 12 shows, a porous insulating film 23 having pores 22 is formed on a semiconductor substrate 21. Next, a resist pattern 24 is formed on the porous insulating film 23 to form the structure shown in FIG. 13. Then, the porous insulating film 23 is subjected to dry etching using a resist pattern 24 as a mask to form a trench 25 for the copper wiring in the porous insulating film 23. After removing no longer required resist pattern 24 by ashing, cleaning is performed using a cleaning solution to form the structure shown in FIG. 14. Then, a barrier-metal film 26 is formed on the inner surface of the trench 25, and a copper layer 27 is buried. By the above-described steps, a copper wiring shown in FIG. 15 is formed.
However, the porous insulating film has the following problems due to the presence of pores. Specifically, in the above-described dry etching and ashing steps, the porous insulating film is easily undergone charging damage by plasma. Also in the cleaning step, the cleaning solution penetrates easily into the porous insulating film. Thereby, the characteristics of the porous insulating film as an interlayer insulating film is degraded, causing problems of the lowered electrical properties and the lowered reliability of the semiconductor device.